1. Field of the Invention
The present invention relates to a method for driving a plasma display panel.
2. Description of the Related Background Art
Recently, with the increase in the screen size of display apparatuses, thin-shape display apparatuses have become available, and various kinds of thin-shape display devices have been put into practical use. Amongst such thin-shape display devices, much attention is now being paid to AC (alternating current) type of plasma display panels.
FIG. 1 is a schematic diagram of a plasma display apparatus comprising such a plasma display panel and a driver to drive this display panel.
In FIG. 1, the plasma display panel PDP 10 comprises m column electrodes D1-Dm as data electrodes, and n row electrodes X1-Xn and n row electrodes Y1-Yn which intersect each of the column electrodes. One pair of Xi (1xe2x89xa6ixe2x89xa6n) and Yi (1xe2x89xa6ixe2x89xa6n) of the row electrodes X1-Xn and Y1-Yn forms one display line of the PDP 10. The column electrodes D and the row electrodes X and Y are arranged face each other with a discharge space containing discharge gas therebetween. A discharge cell corresponding to a picture element is formed at the intersection of each row electrode and each column electrode with the discharge space between them.
Each discharge cell emits light by the discharge effect, so each cell can have only two states, a xe2x80x9clight emittingxe2x80x9d state or a xe2x80x9cnon-light emittingxe2x80x9d state. That is, each discharge cell exhibits only two gradations, minimum brightness (non-light emitting state) and maximum brightness (light emitting state).
Therefore, the driver 100 performs gradation drive by using the subfield method in order to display brightness of half tone corresponding to a video signal supplied to the PDP 10. In the subfield method, an input video signal is converted, for example, into 4-bit picture element data corresponding to each picture element. The display period of one field is divided into four subfields SF1-SF4 so that each subfield corresponds to each bit digit of said picture element data, as is shown in FIG. 2. As indicated in FIG. 2, a light emitting frequency (or light emitting period) corresponding to the weight of the subfield is allocated to each subfield.
FIG. 3 shows various kinds of driving pulses to be supplied to the row electrodes and the column electrodes of the PDP 10 in each subfield shown in FIG. 2, and the pulse supply timing.
As shown in FIG. 3, the driver 100 supplies negative reset pulses RPx to the row electrodes X1-Xn, and positive reset pulses RPy to the row electrodes Y1-Yn. In response to the supply of these reset pulses RPX and RPY, all the discharge cells of the PDP 10 are reset and discharged and a predetermined wall charge is uniformly formed in each discharge cell. Thus, all the discharge cells in the PDP 10 are initialized to the xe2x80x9cnon-light emitting cellxe2x80x9d state (simultaneous reset process Rc).
Next, the driver 100 separates each bit digit of said 4-bit picture element data into the subfields SF1-SF4, and generates picture element data pulses having a pulse voltage corresponding to the logical level of said bit. For example, during the picture element data write process Wc for the subfield SF1, the driver 100 generates picture element pulses having a pulse voltage corresponding to the logical level of the first bit of said picture element data. In this case, the driver 100 generates picture element data pulses of high voltage when the logical level of the first bit is xe2x80x9c1xe2x80x9d and it generates picture element data pulses of low voltage (O volt) when said logical level is xe2x80x9c0xe2x80x9d. In addition, the driver 100 supplies said picture element data pulses to the column electrodes D1-Dm sequentially as picture element data pulse groups DP1-DPn for one display line corresponding to one of the first-nth display lines. In addition, the driver 100 generates negative scanning pulses SP as shown in FIG. 3 in synchronization with the supply timing of each picture element data pulse group DP, and supplies the scanning pulses SP to the row electrodes Y1-Yn sequentially. In this case, only a discharge cell at the intersection of a display line to which said scanning pulses SP were supplied and a xe2x80x9ccolumnxe2x80x9d to which the picture element data pulses of high voltage were supplied discharges (selective erasing discharge), and the wall charge in that discharge cell disappears. Thus, the discharge cell which was initialized to a xe2x80x9clight emission cellxe2x80x9d state during said simultaneous reset process Rc is shifted to a xe2x80x9cnon-light emission cell state. On the other hand, a discharge cell to which the scanning pulses SP were supplied and at the same time the low voltage picture element data pulses were also supplied does not generate the above-mentioned selective erasing discharge. Thus, this discharge cell is sustained at the state initialized during said simultaneous reset process Rc, namely, at the xe2x80x9clight emission cellxe2x80x9d state. Therefore, each discharge cell of the PDP 10 is set to the xe2x80x9clight emission cellxe2x80x9d state or the xe2x80x9cnon-light emission cellxe2x80x9d state in accordance with the picture element data corresponding to the input video signal (picture element data write process Wc).
Next, the driver 100 supplies sustaining pulses IPX and IPY as shown in FIG. 3 to the row electrodes X1-Xn and the row electrodes Y1-Yn alternately and repeatedly. When the supply frequency during the light emission sustaining process Ic of the subfield SF-1 is xe2x80x9c1xe2x80x9d, the supply frequency (or period) of the sustaining pulses IPX and IPY during the sustaining process Ic of each subfield SF1-SF4 shown in FIG. 2 is as follows.
SF1:1
SF2:2
SF3:4
SF4:8
In this case, only a discharge cell in which a wall charge remains in its discharge space, namely, only a xe2x80x9clight emission cellxe2x80x9d, discharges (discharge for sustaining light emission cell state) each time such sustaining pulses IPX and IPy are supplied to such a cell. That is, only a discharge cell which did not produce a selective erasing discharge during said picture element data write process Wc emits light due to said sustaining discharge repeatedly by a frequency allocated to each subfield as described above, and sustains its light emitting state (light emission sustaining process Ic).
Finally, the driver 100 supplies erasing pulses EP shown in FIG. 3 to the row electrodes Y1-Yn simultaneously. Because of the supply of such erasing pulses EP, erasing discharge takes place in all the discharge cells of the PDP 10, and the wall charge remaining in these discharge cells disappears (erasing process E).
A series of such processes as said simultaneous reset process Rc, picture element data write process Wc, light emission sustaining process Ic and erasing process E are executed for each of the subfields SF1-SF4 shown in FIG. 2. By such driving, the light due to the sustaining discharge is emitted by a frequency corresponding to the brightness level of the input video signal throughout the display period of one field. In this case, an intermediate tone corresponding to the light emission frequency is visible. Therefore, as is shown in FIG. 2, by tone-driving based on the four subfields SF1-SF4, intermediate tones xe2x80x9c0xe2x80x9d to xe2x80x9c15xe2x80x9d can be displayed in 16 stages (16 tones).
If the number of divided subfields is increased, the number of tones which can be represented is also increased, so an image of higher quality can be displayed. For example, narrowing the width of each of the sustaining pulses IP which are supplied repeatedly as is shown in FIG. 3 decreases the time required for each light emission sustaining process Ic, so the number of subfields can be increased by using the extra time made available.
However, narrowing the width of the sustaining pulses IP may result in erroneous discharge, especially when the amount of charged particles remaining in the discharge space of each discharge cell is small. Therefore, it is impossible to narrow the pulse width beyond a certain limit.
An object of the present invention is to provide a method for driving a plasma display panel which can display an image of high quality with many tone stages without causing discharge cells to discharge erroneously.
A method for driving a plasma display panel according to the present invention is a method for driving a plasma display panel by driving the tone of said plasma display panel in which each discharge cell is formed at each intersection of a plurality of row electrodes corresponding to a display line and a plurality of column electrodes intersecting with said row electrodes in accordance with a video signal, comprising: in each of a plurality of subfields constituting a display period of one field of said video signal, a picture element data write process for supplying scanning pulses to each of said row electrodes sequentially, which generate selective discharge for setting each of said discharge cells to the light emission cell state or non-light emission cell state in accordance with the picture element data corresponding to said video signal; and a light emission sustaining process for supplying sustaining pulses which generate sustaining discharge only in said discharge cells in said light emission cell state to each of said row electrodes by a frequency corresponding to the weight of each of said subfields; wherein the width of the first sustaining pulse of said sustaining pulses to be supplied first during said light emission sustaining process is set wider than that of the subsequent sustaining pulses, and the width of said first sustaining pulse is narrowed in accordance with the frequency of said sustaining discharge occurring immediately before the supply of said first sustaining pulse during the display period of one field.